BCD to 7 Segment Simple Code

This is a very basic BCD to 7 segment decoder implementation, written using VHDL code. I use Altera Max II Plus 10.2 to compile and simulate this code. The simulation timing diagram is on below the code

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY bcd7segment IS
port ( bcd : IN STD_LOGIC_VECTOR (3 downto 0);
leds : OUT STD_LOGIC_VECTOR (1 to 7));
END bcd7segment;

ARCHITECTURE Behavior OF bcd7segment IS
BEGIN
PROCESS (bcd)
BEGIN
CASE bcd IS
WHEN "0000" => leds <="1111110"; WHEN "0001" => leds <="0110000"; WHEN "0010" => leds <="1101101"; WHEN "0011" => leds <="1111001"; WHEN "0100" => leds <="0110011"; WHEN "0101" => leds <="1011011"; WHEN "0110" => leds <="1011111"; WHEN "0111" => leds <="1110000"; WHEN "1000" => leds <="1111111"; WHEN "1001" => leds <="1110011"; WHEN OTHERS => leds <="-------"; END CASE; END PROCESS; END Behavior;

With simulation result :







(Click to view full size picture)

Well that's my first project using VHDL, while quite elementary, it introduces me into VHDL.