VHDL - 4 bit register using DFF

This is a 4-bit register simulation using D-Flipflop that we made before. It uses them as a component, and we use Port Mapping to access them. Here is the code for the work package :

LIBRARY ieee;
USE ieee.std_logic_1164.all;

PACKAGE package_dff IS
COMPONENT dff
PORT ( D : IN STD_LOGIC;
Clock, Resetn : IN STD_LOGIC;
Q : OUT STD_LOGIC);
END COMPONENT;
END package_dff;

And this is the code for the 4-bit register that use the DFF :

LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
USE work.package_dff.all;

ENTITY reg4bit IS
PORT ( D : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
Resetn, Clock : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
END reg4bit;

ARCHITECTURE Structure OF reg4bit IS
BEGIN
dff01 : dff1 PORT MAP (D(3),Clock,Resetn,Q(3));
dff02 : dff1 PORT MAP (D(2),Clock,Resetn,Q(2));
dff03 : dff1 PORT MAP (D(1),Clock,Resetn,Q(1));
dff04 : dff1 PORT MAP (D(0),Clock,Resetn,Q(0));
END Structure;

The simulation result :

(click to enlarge)

When the inputs given on each D are "1011", the output of the register is also "1011", therefore ir stores the data, and it resets to "0000" when the input resetn is set to 0.

Simple D-Flipflop (VHDL)

This is a simple D-Flipflop implementation using VHDL. The program I use is Altera Max II Plus 10.2. The simulation result is below the code

VHDL Code:

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY dff IS
PORT ( D : IN STD_LOGIC;
Clock, Resetn : IN STD_LOGIC;
Q : OUT STD_LOGIC);
END dff;

ARCHITECTURE Behavior OF dff IS
BEGIN
PROCESS (Clock, Resetn)
BEGIN
IF Clock'EVENT AND Clock = '1' THEN
IF Resetn = '0' THEN
Q <= '0'; ELSE Q <= D; END IF; END IF; END PROCESS; END Behavior;


Here is the simulation result :

(Click to enlarge)

This is quite simple, I don't think I should explain how this works. It simply does what D-Flipflops do, that is maintaining an input on D within the clock cycle through the output Q. The output will reset to 0 when the input reset is given within the positive clock edge.

This DFF is used as a component on another project of mine, that is 4-bit register using DFF. Check that out!

BCD to 7 Segment Simple Code

This is a very basic BCD to 7 segment decoder implementation, written using VHDL code. I use Altera Max II Plus 10.2 to compile and simulate this code. The simulation timing diagram is on below the code

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY bcd7segment IS
port ( bcd : IN STD_LOGIC_VECTOR (3 downto 0);
leds : OUT STD_LOGIC_VECTOR (1 to 7));
END bcd7segment;

ARCHITECTURE Behavior OF bcd7segment IS
BEGIN
PROCESS (bcd)
BEGIN
CASE bcd IS
WHEN "0000" => leds <="1111110"; WHEN "0001" => leds <="0110000"; WHEN "0010" => leds <="1101101"; WHEN "0011" => leds <="1111001"; WHEN "0100" => leds <="0110011"; WHEN "0101" => leds <="1011011"; WHEN "0110" => leds <="1011111"; WHEN "0111" => leds <="1110000"; WHEN "1000" => leds <="1111111"; WHEN "1001" => leds <="1110011"; WHEN OTHERS => leds <="-------"; END CASE; END PROCESS; END Behavior;

With simulation result :







(Click to view full size picture)

Well that's my first project using VHDL, while quite elementary, it introduces me into VHDL.