MIPS - Determinant of 2x2 matrix

This is the first of 3 Problems I got regarding the MIPS. The problems are given to make the students get used to MIPS assembly language. The simulation is performed using MIPS32 Simulator called PC SPIM, which can be acquired freely at http://pages.cs.wisc.edu/~larus/spim.html

The first problem is :

Create a program to compute determinant of a 2x2 matrix. Remember how a a 2-D array is
stored in memory. Result is stored in memory. Use integer only operations and assume all
result are 32-bit.

The idea is to put the matrix into the memory in the following order : [a00,a01,a10,a11], then do a calculation of determinant. If the result is negative than it must be inverted (because the absolute mark).
Here is the resulting code:

.data 0x10010000
.word 2,1,3,4
.space 4
.text
.globl main

main: addu $s0,$ra,$0
lui $s1,0x1001
lw $t0, 0($s1)
lw $t1, 4($s1)
lw $t2, 8($s1)
lw $t3, 12($s1)
mult $t0,$t3
mflo $s2
mult $t1,$t2
mflo $s3
sub $s4,$s2,$s3
slt $t4,$s4,$0
beq $t4,$0,oke
nor $s4,$s4,$0
addi $s4,$s4,1
oke: sw $s4,16($s1)
addu $ra,$0,$s0
jr $ra

MIPS Assembly Introduction

This is an introduction program to get used into MIPS Assembly language. The codes compiled and simulated using PC SPIM ver 7.00. With this little program, we can see what happens in the registers and memory, debugging the code line per line, etc. It also has a console so that the input/output may be displayed.

The first simple program is to convert Farenheit temperature degree into Celcius temperature degree. The code is :

.data
enter: .asciiz "Enter temperature in farenheit: "
cel1: .asciiz "It's the same as "
cel2: .asciiz " celcius\n"
.text
.globl main
main: addu $s0, $ra, $0
li $v0,4
la $a0,enter
syscall
li $v0,5
syscall
add $t0,$0,$v0
sub $t0,$t0,32
li $t1,5
li $t2,9
mult $t0,$t1
mflo $t3
divu $t3,$t2
mflo $t4
li $v0,4
la $a0,cel1
syscall
add $a0,$0,$t4
li $v0,1
syscall
li $v0,4
la $a0,cel2
syscall
addu $ra, $0, $s0
jr $ra

it uses syscall to display some text on the console, as well as taking inputs from there. The parameters for syscall is regulated by register $v0.

The simulation result is like this :
(click to enlarge)

Resource links

A few interesting resource links :

• Funny Quotes - Your source for funny quotes and quotations from thousands of famous people.
• Science Technology - Science and Technology Articles and News Every Day.
• Mypapit Free and Open Source - Tips, Tutorial and Open Source software reviews
• Jon Griffin's Personal Site - Articles on programming, cooking, brewing and more.
  

VHDL - 4 bit register using DFF

This is a 4-bit register simulation using D-Flipflop that we made before. It uses them as a component, and we use Port Mapping to access them. Here is the code for the work package :

LIBRARY ieee;
USE ieee.std_logic_1164.all;

PACKAGE package_dff IS
COMPONENT dff
PORT ( D : IN STD_LOGIC;
Clock, Resetn : IN STD_LOGIC;
Q : OUT STD_LOGIC);
END COMPONENT;
END package_dff;

And this is the code for the 4-bit register that use the DFF :

LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
USE work.package_dff.all;

ENTITY reg4bit IS
PORT ( D : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
Resetn, Clock : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
END reg4bit;

ARCHITECTURE Structure OF reg4bit IS
BEGIN
dff01 : dff1 PORT MAP (D(3),Clock,Resetn,Q(3));
dff02 : dff1 PORT MAP (D(2),Clock,Resetn,Q(2));
dff03 : dff1 PORT MAP (D(1),Clock,Resetn,Q(1));
dff04 : dff1 PORT MAP (D(0),Clock,Resetn,Q(0));
END Structure;

The simulation result :

(click to enlarge)

When the inputs given on each D are "1011", the output of the register is also "1011", therefore ir stores the data, and it resets to "0000" when the input resetn is set to 0.

Simple D-Flipflop (VHDL)

This is a simple D-Flipflop implementation using VHDL. The program I use is Altera Max II Plus 10.2. The simulation result is below the code

VHDL Code:

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY dff IS
PORT ( D : IN STD_LOGIC;
Clock, Resetn : IN STD_LOGIC;
Q : OUT STD_LOGIC);
END dff;

ARCHITECTURE Behavior OF dff IS
BEGIN
PROCESS (Clock, Resetn)
BEGIN
IF Clock'EVENT AND Clock = '1' THEN
IF Resetn = '0' THEN
Q <= '0'; ELSE Q <= D; END IF; END IF; END PROCESS; END Behavior;


Here is the simulation result :

(Click to enlarge)

This is quite simple, I don't think I should explain how this works. It simply does what D-Flipflops do, that is maintaining an input on D within the clock cycle through the output Q. The output will reset to 0 when the input reset is given within the positive clock edge.

This DFF is used as a component on another project of mine, that is 4-bit register using DFF. Check that out!

BCD to 7 Segment Simple Code

This is a very basic BCD to 7 segment decoder implementation, written using VHDL code. I use Altera Max II Plus 10.2 to compile and simulate this code. The simulation timing diagram is on below the code

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY bcd7segment IS
port ( bcd : IN STD_LOGIC_VECTOR (3 downto 0);
leds : OUT STD_LOGIC_VECTOR (1 to 7));
END bcd7segment;

ARCHITECTURE Behavior OF bcd7segment IS
BEGIN
PROCESS (bcd)
BEGIN
CASE bcd IS
WHEN "0000" => leds <="1111110"; WHEN "0001" => leds <="0110000"; WHEN "0010" => leds <="1101101"; WHEN "0011" => leds <="1111001"; WHEN "0100" => leds <="0110011"; WHEN "0101" => leds <="1011011"; WHEN "0110" => leds <="1011111"; WHEN "0111" => leds <="1110000"; WHEN "1000" => leds <="1111111"; WHEN "1001" => leds <="1110011"; WHEN OTHERS => leds <="-------"; END CASE; END PROCESS; END Behavior;

With simulation result :







(Click to view full size picture)

Well that's my first project using VHDL, while quite elementary, it introduces me into VHDL.

Welcome to my projects collection site!

Hi there!

This is my first post.. I made this blog to put some (if not all) of my past and current project that I got as an assignment from my college Institut Teknologi Bandung. The projects usually are simple task that could be solved using simple logic.

Most of the projects are about logic design using VHDL, simple programming using C/C++, and some simple use of MIPS Assembly Language. And a few others too if I can conclude :)

I can't post all of them in at a time, but I will regularly post them there.. If you got any interesting ideas around these projects, feel free to contact me or at least leave a comment.

Thanks!