VHDL - 4 bit register using DFF

This is a 4-bit register simulation using D-Flipflop that we made before. It uses them as a component, and we use Port Mapping to access them. Here is the code for the work package :

LIBRARY ieee;
USE ieee.std_logic_1164.all;

PACKAGE package_dff IS
COMPONENT dff
PORT ( D : IN STD_LOGIC;
Clock, Resetn : IN STD_LOGIC;
Q : OUT STD_LOGIC);
END COMPONENT;
END package_dff;

And this is the code for the 4-bit register that use the DFF :

LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
USE work.package_dff.all;

ENTITY reg4bit IS
PORT ( D : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
Resetn, Clock : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
END reg4bit;

ARCHITECTURE Structure OF reg4bit IS
BEGIN
dff01 : dff1 PORT MAP (D(3),Clock,Resetn,Q(3));
dff02 : dff1 PORT MAP (D(2),Clock,Resetn,Q(2));
dff03 : dff1 PORT MAP (D(1),Clock,Resetn,Q(1));
dff04 : dff1 PORT MAP (D(0),Clock,Resetn,Q(0));
END Structure;

The simulation result :

(click to enlarge)

When the inputs given on each D are "1011", the output of the register is also "1011", therefore ir stores the data, and it resets to "0000" when the input resetn is set to 0.