Simple D-Flipflop (VHDL)

This is a simple D-Flipflop implementation using VHDL. The program I use is Altera Max II Plus 10.2. The simulation result is below the code

VHDL Code:

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY dff IS
PORT ( D : IN STD_LOGIC;
Clock, Resetn : IN STD_LOGIC;
Q : OUT STD_LOGIC);
END dff;

ARCHITECTURE Behavior OF dff IS
BEGIN
PROCESS (Clock, Resetn)
BEGIN
IF Clock'EVENT AND Clock = '1' THEN
IF Resetn = '0' THEN
Q <= '0'; ELSE Q <= D; END IF; END IF; END PROCESS; END Behavior;


Here is the simulation result :

(Click to enlarge)

This is quite simple, I don't think I should explain how this works. It simply does what D-Flipflops do, that is maintaining an input on D within the clock cycle through the output Q. The output will reset to 0 when the input reset is given within the positive clock edge.

This DFF is used as a component on another project of mine, that is 4-bit register using DFF. Check that out!